1. Field of Invention
The present invention relates generally to designing integrated circuits, and more particularly relates to methods for verifying that a given circuit layout design conforms to predetermined design constraints.
2. State of the Art
Generally speaking, techniques are known for verifying that a circuit layout (e.g., standard cell) conforms with predetermined design constraints. For example, design rule checking techniques are known for verifying that the geometries (e.g., conductive or non-conductive paths) included in all layers of a given integrated circuit layout comply with predetermined minimum width requirements. At best, these techniques can verify that all geometries in a given layer of an integrated circuit layout satisfy the minimum width constraint. It is important to verify that all paths in the circuit layout comply with minimum width requirements to avoid problems such as metal migration, voltage division, timing problems and so forth.
There is a continual effort to reduce integrated circuit size, and to increase operational speed. For example, to increase signal processing speed it would be desirable to increase transistor power. This entails providing higher V.sub.dd (drain) and V.sub.ss (source) currents. Higher V.sub.dd and V.sub.ss currents require that the paths conducting these currents be designed larger (e.g., wider design specifications) to avoid problems such as metal migration. However, no techniques currently exist for separately verifying proper design of this wider path. That is, no practical way exists for verifying that a path between two arbitrary nodes satisfies predetermined minimum width constraints which are different from minimum width constraints for remaining portions of the circuit layout. Thus, the probability of errors in the design is great.